A few weeks ago, I saw a post over on EE Times on Network on Chip (NOC) The main point the post made was that System on Chip (SOC) designers can optimize their products by incorporating NOC interconnect IP. As the article was written by the CEO of a company that makes interconnect fabric IP, the point is not surprising. Still, it’s a good one.
One of the benefits of using NOC technology is higher bandwidth, and this is one of the reasons behind Critical Link’s decision to build a System on Module – the MitySOM-5CSX – based on Altera’sCyclone V SOC. With the Cyclone V,the FPGA and the ARM have been put into the same silicon (die) with interconnect. The higher bandwidth this provides offers a tremendous advantage from an application point of view, allowing us today to easily move 1 GB of data – we could go even higher – between the ARM cores and the FPGA fabric.
In the past, we were limited to 400MB/s using external interconnect. And even that 400 MB/s number is only theoretical; it’s not really achievable.
TI has also embraced the NOC idea with their Keystone architecture. Their interconnect, which they have named TeraNet allows re-use of TeraNet compatible IP blocks, which definitely speeds up time to market, another advantage of the NOC approach. Another advantage of what TI is doing with these re-usable blocks is that the initial software driver for a particular IP block will not always support all the features of the IP block, but over time the drivers evolve and become more robust and feature rich as the IP block gets used in more and more devices. A definite plus as the silicon vendors continue to work on their software strategy, which is far and away the long pole in the tent for new product development these days.
Higher bandwidth and speedier time-to-market are just two of the NOC advantages. A smaller die size, lower power consumption, increased productivity.
Overall, they’re pretty much the same advantages you get with a Critical Link System on Module…