This is the second in a series of blog posts based on a series of articles by Rob Oshana and Mark Kraeling on “Optimizing Embedded Software for Power Efficiency” that ran in Embedded.com in May.
Their second article focused on optimizing “clock control and power features provided in the microprocessor peripheral circuits,” and was primarily oriented towards our friend the DSP, as used in two different types of apps with different power-consumption profiles: an MP3 player and a cell phone.
For both of these power profiles, software-enabled low-power modes (modes/features/ controls) are used to save power, and the question for the programmer is how to use them efficiently… The most common modes available consist of power gating, clock gating, voltage scaling, and clock scaling. (Source: Embedded.com)
Power gating “uses a current switch to cut off a circuit from its power supply rails during standby mode, to eliminate static leakage when the circuit is not in use.” Power gating can sometimes to be used to save power by shutting off unused peripherals.
Clock gating:
…shuts down clocks to a circuit or portion of a clock tree in a device. As dynamic power is consumed during state change triggered by clock toggling…clock gating enables the programmer to cut dynamic power through the use of a single (or a few) instructions. Clocking of a processor core like a DSP is generally separated into trees stemming from a main clock PLL into various clock domains as required by design for core, memories, and peripherals, and DSPs generally enable levels of clock gating in order to customize a power-saving solution.
The article then goes into detail on low-power modes in a couple of different DSPs, the Freescale MCS815x and the Texas Instruments C6000. (We use C6000 DSP in our MityDSP-L138 SoM, which features TI’s OMAP-L138.)
Next, the article gets into clock and voltage control/scaling. One method of voltage scaling is using a voltage regulator module to monitor and update voltage ID parameters. There’s a lot of detail on the pros and cons of clock scaling.
Admittedly, I’m not doing justice to the information – including very detailed examples – that’s provided in these articles. Just trying to give a sense of what’s covered – and to encourage those who want a quick course in taking a software approach to power efficiency to give them all a full read.
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The full series of articles is linked here:
Optimizing embedded software for power efficiency: Part 1 – Measuring power
Optimizing embedded software for power efficiency: Part 2 – Minimizing hardware power
Optimizing embedded software for power efficiency: Part 3 – Optimizing data flow and memory
Optimizing embedded software for power efficiency: Part 4 – Peripheral and algorithmic optimization
They are all excerpted from Oshana’s and Kaeling’s book, Software Engineering for Embedded Systems.