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Working with your PCB Manufacturer

One of the principal reasons that developers choose to embed a Critical Link System-on-Module in their applications is to reduce their risk. A big part of that risk is what happens when a board moves from design to manufacture. If it turns out that you have design problems, this can prove very costly, losing you both time and money. It will typically take a month or so to get you from board release to having your assembled board back in your hands for test. If your find that the design was flawed in a major way, it’s back to the drawing board. And another month or so back in manufacture.

As I said, this can all add up in terms of time, and manufacturing costs. (Unfortunately, manufacture of a flawed design costs just as much as a perfect design)

There was an interesting article relating to this topic by Zulki Khan of NexLogic (PCB design and fabrication specialists) on embedded.com. The article provided a set of tips outlining “ways to avoid embedded PCB engineering change orders.” Although Zulki’s list is by no means exhaustive, it’s definitely worth a read.

The first tip is to be careful in your component selection. This is something that Critical Link understands quite well. We’re extremely careful about the components –  ARM processors, DSP’s, FPGA’s, WiFi, software – that go into our SoMs. As are our customers, for whom our SoMs are components.

The second area that Zulki calls out is memory selection, noting that the specs are “ever-changing”, and warns the developers should definitely keep an eye out for DDR4, which will be taking off soon. (I know that we’re keeping an eye on it.)

Moisture sensitivity levels (MSL) are also important to factor in. If not correctly identified, your manufacturer “won’t take the MSL information into account and circuitry will not work properly in the field. This is especially true if MSL levels like 3, 4, or 5 exist. As a result, baking might not be properly performed and moisture might creep in, resulting in ECOs.”

Zulki also has a warning about making sure that you’ve carefully considered your design for test (DFT)test points.

…and the angle at which the probe comes in to touch vias, pads, and other test points.

When DFT has not been allowed for early in the initial design, testing becomes a major issue and ECOs are generated. In some extreme cases, a re-spin is required to address the issue because ECOs may not work.

Paying attention to cooling, heat sinks, and the coefficient of thermal expansion  round out Zulki’s list, which is a good one. However, in our experience, Zulki’s list is really just the tip of the iceberg! Stay tuned for more on this topic.